TN

Takuo Nakaki

NE Nec: 2 patents #5,510 of 14,502Top 40%
Overall (All Time): #2,217,106 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6434722 Method of changing logic circuit portion into gated clock portion and recording medium storing a program for carrying out the method Masamichi Kawarabayashi 2002-08-13
5801956 Method for deciding the feasibility of logic circuit prior to performing logic synthesis Hajime Kawamura, Takeharu Nemoto 1998-09-01