Issued Patents All Time
Showing 76–100 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5596542 | Semiconductor memory device having dual word line configuration | Satoshi Utsugi, Isao Naritake | 1997-01-21 |
| 5581205 | Semiconductor device capable of assembling adjacent sub chips into one chip | — | 1996-12-03 |
| 5463591 | Dual port memory having a plurality of memory cell arrays for a high-speed operation | Yoshiharu Aimoto | 1995-10-31 |
| 5436910 | Dynamic random access memory device having a parallel testing mode for producing arbitrary test pattern | Toshio Takeshima, Isao Naritake | 1995-07-25 |
| 5416368 | Level conversion output circuit with reduced power consumption | — | 1995-05-16 |
| 5414660 | Double word line type dynamic RAM having redundant sub-array of cells | Isao Naritake, Tatsuya Matano | 1995-05-09 |
| 5406526 | Dynamic random access memory device having sense amplifier arrays selectively activated when associated memory cell sub-arrays are accessed | Mamoru Fujita, Isao Naritake | 1995-04-11 |
| 5400291 | Dynamic RAM | Isao Naritake | 1995-03-21 |
| 5375096 | Data bus selector/control circuit for dynamic ram | — | 1994-12-20 |
| 5373477 | Integrated circuit device having step-down circuit for producing internal power voltage free from overshoot upon voltage drop of external power voltage | — | 1994-12-13 |
| 5369620 | Dynamic random access memory device having column selector for selecting data lines connectable with bit lines | — | 1994-11-29 |
| 5361000 | Reference potential generating circuit | Yasuji Koshikawa | 1994-11-01 |
| 5357474 | Dynamic random access memory device having precharge circuit for intermittently and selectively charging data line pairs | Tatsuya Matano, Hiroshi Takada | 1994-10-18 |
| 5352935 | Semiconductor integrated circuit device with internal voltage controlling circuit | Ryuji Yamamura, Takahiro Hara | 1994-10-04 |
| 5337270 | Semiconductor dynamic memory | Koji Kawata | 1994-08-09 |
| 5329168 | Semiconductor integrated circuit device equipped with substrate biasing system selectively powered from internal and external power sources | Yasuji Koshikawa, Takahiro Hara | 1994-07-12 |
| 5319601 | Power supply start up circuit for dynamic random access memory | Koji Kawata, Takahiro Hara | 1994-06-07 |
| 5319302 | Semiconductor integrated circuit device having voltage regulating unit for variable internal power voltage level | Yasuji Koshikawa, Takahiro Hara | 1994-06-07 |
| 5305265 | Semiconductor memory device having column selection circuit activated subsequently to sense amplifier after first or second period of time | — | 1994-04-19 |
| 5289061 | Output gate for a semiconductor IC | Yasuji Koshikawa, Ryuji Yamamura | 1994-02-22 |
| 5287011 | Power-on detecting circuit desirable for integrated circuit equipped with internal step-down circuit | Yasuji Koshikawa, Takahiro Hara | 1994-02-15 |
| 5285412 | Semiconductor memory device with step-down transistor for external signal | — | 1994-02-08 |
| 5272673 | Dynamic random access memory device with build-in test mode discriminator for interrupting electric power to row address decoder and driver for transfer gates | — | 1993-12-21 |
| 5270584 | Semiconductor integrated circuit | Yasuji Koshikawa, Takahiro Hara | 1993-12-14 |
| 5184035 | Bootstrap circuit incorporated in semiconductor memory device for driving word lines | — | 1993-02-02 |