| 8830719 |
One-time programmable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof |
Hiroyuki Furukawa |
2014-09-09 |
| 8432717 |
One-time programmable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof |
Hiroyuki Furukawa |
2013-04-30 |
| 8174922 |
Anti-fuse memory cell and semiconductor memory device |
— |
2012-05-08 |
| 7532059 |
Semiconductor integrated circuit device and substrate bias controlling method |
— |
2009-05-12 |
| 6731547 |
Semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other |
— |
2004-05-04 |
| 6601197 |
Semiconductor memory device |
— |
2003-07-29 |
| 6577543 |
Semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other |
— |
2003-06-10 |
| 6339560 |
Semiconductor memory based on address transitions |
— |
2002-01-15 |
| 6208563 |
Semiconductor memory device which continuously performs read/write operations with short access time |
— |
2001-03-27 |
| 6151237 |
DRAM having each memory cell storing plural bit data |
— |
2000-11-21 |
| 6130845 |
Dynamic type semiconductor memory device having function of compensating for threshold value |
Tetsuya Ootsuki |
2000-10-10 |
| 6097620 |
Multi-value dynamic semiconductor memory device having twisted bit line pairs |
— |
2000-08-01 |
| 6038184 |
Semiconductor memory device having internal timing generator shared between data read/write and burst access |
— |
2000-03-14 |
| 5995403 |
DRAM having memory cells each using one transfer gate and one capacitor to store plural bit data |
— |
1999-11-30 |
| 5978255 |
Semiconductor memory device stably storing multiple-valued data without a decrease in operation margin |
— |
1999-11-02 |
| 5732026 |
Semiconductor memory device including main/sub-bit line arrangement |
Tadahiko Sugibayashi |
1998-03-24 |
| 5631872 |
Low power consumption semiconductor dynamic random access memory device by reusing residual electric charge on bit line pairs |
Tadahiko Sugibayashi, Satoshi Utsugi, Tatsunori Murotani |
1997-05-20 |
| 5596542 |
Semiconductor memory device having dual word line configuration |
Tadahiko Sugibayashi, Satoshi Utsugi |
1997-01-21 |
| 5436910 |
Dynamic random access memory device having a parallel testing mode for producing arbitrary test pattern |
Toshio Takeshima, Tadahiko Sugibayashi |
1995-07-25 |
| 5414660 |
Double word line type dynamic RAM having redundant sub-array of cells |
Tadahiko Sugibayashi, Tatsuya Matano |
1995-05-09 |
| 5406526 |
Dynamic random access memory device having sense amplifier arrays selectively activated when associated memory cell sub-arrays are accessed |
Tadahiko Sugibayashi, Mamoru Fujita |
1995-04-11 |
| 5400291 |
Dynamic RAM |
Tadahiko Sugibayashi |
1995-03-21 |