| 8724683 |
Communication testing circuit, electronic device, receiving circuit, transmitting circuit, semiconductor integrated circuit, and wafer |
— |
2014-05-13 |
| 7468957 |
Canceller circuit and controlling method |
— |
2008-12-23 |
| 7463171 |
Parallel conversion circuit |
— |
2008-12-09 |
| 7386083 |
Phase comparator having a flip-flop circuit and a logic circuit |
— |
2008-06-10 |
| 6888389 |
Digital control variable delay circuit which is hardly susceptible to noise |
— |
2005-05-03 |
| 6856658 |
Digital PLL circuit operable in short burst interval |
Masaki Sato |
2005-02-15 |
| 6614863 |
Bit synchronization method and bit synchronization device |
— |
2003-09-02 |
| 6556640 |
Digital PLL circuit and signal regeneration method |
— |
2003-04-29 |
| 6549571 |
Circuitry and method for duty measurement |
— |
2003-04-15 |
| 6278755 |
Bit synchronization circuit |
Yasushi Aoki, Minoru Kayano, Yuuji Takahashi, Atsushi Katayama |
2001-08-21 |
| 6236696 |
Digital PLL circuit |
Yasushi Aoki, Masaki Satoh, Satoko Murakami, Kiyoshi Mikami |
2001-05-22 |
| 6137336 |
Circuit and method for generating multiphase clock |
Hiroki Teramoto |
2000-10-24 |
| 6002731 |
Received-data bit synchronization circuit |
Yasushi Aoki |
1999-12-14 |
| 5909473 |
Bit synchronizing circuit |
Yasushi Aoki, Atsushi Katayama |
1999-06-01 |
| 5877658 |
Phase locked loop |
— |
1999-03-02 |
| 5687203 |
Digital phase locked loop circuit |
— |
1997-11-11 |
| 5528198 |
Clock signal extraction apparatus using VCO having plurality of selectable phase shifted outputs |
Yasushi Aoki |
1996-06-18 |
| 5467041 |
Variable delay buffer circuit |
Yasushi Aoki |
1995-11-14 |