Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8106703 | Booster circuit | Yoshihiro NAGAI, Masahiko Kashimura, Masato Taki, Norihiro Honda, Kazushi Yamanaka | 2012-01-31 |
| 8004902 | Nonvolatile semiconductor memory device | Masahiko Kashimura, Yoshihiro NAGAI, Masato Taki, Norihiro Honda, Kazushi Yamanaka | 2011-08-23 |
| 7385856 | Non-volatile memory device and inspection method for non-volatile memory device | Hirofumi Oga, Masahiko Kashimura | 2008-06-10 |
| 6177824 | Level shifting circuit | — | 2001-01-23 |
| 6128230 | Semiconductor memory with PN junction potential reduction in a writing mode | — | 2000-10-03 |
| 6115288 | Semiconductor memory device | Hiroyuki Kobatake, Satoru Oku, Kazuaki Kato, Masaki Kaneko | 2000-09-05 |
| 6111792 | Non-volatile semiconductor memory device for selective cell flash erasing/programming | Satoru Oku, Hiroyuki Kobatake, Kazuaki Kato, Masaki Kaneko | 2000-08-29 |
| 6084387 | Power source circuit for generating positive and negative voltage sources | Masaki Kaneko, Hiroyuki Kobatake, Kazuaki Kato, Satoru Oku | 2000-07-04 |
| 5942808 | Semiconductor device with plural power supply circuits, plural internal circuits, and single external terminal | Masaki Kaneko, Hiroyuki Kobatake, Kazuaki Kato, Satoru Oku | 1999-08-24 |
| 5787037 | Non-volatile memory device which supplies erasable voltage to a flash memory cell | — | 1998-07-28 |
| 5677875 | Non-volatile semiconductor memory device configured to minimize variations in threshold voltages of non-written memory cells and potentials of selected bit lines | Yasushi Yamagata | 1997-10-14 |
| 5499212 | Semiconductor memory device having a bias control circuit for erase voltage blocking transistor | — | 1996-03-12 |
| 5309397 | Read only memory device equipped with output data buffer circuits less affectable by noises on power voltage line | — | 1994-05-03 |