KK

Kiyonori Kajiyana

NE Nec: 2 patents #5,510 of 14,502Top 40%
Overall (All Time): #2,263,578 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
5804505 Method of producing semiconductor device having buried contact structure Yoshiaki Yamada 1998-09-08
5798544 Semiconductor memory device having trench isolation regions and bit lines formed thereover Shuichi Ohya, Masato Sakao, Yoshihiro Takaishi, Takeshi Akimoto, Shizuo Oguro +1 more 1998-08-25