Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6202193 | Apparatus for optimization of circuit design | Koichi Sato | 2001-03-13 |
| 6188934 | Register correspondence method using I/O terminals, determined registers, the number of undetermined registers and self-feedback information to define unique registers | — | 2001-02-13 |
| 6009248 | Delay optimization system to conduct optimization for satisfying delay constraints on the circuit and method therefor | Koichi Sato, Naotaka Maeda, Masamichi Kawarabayashi | 1999-12-28 |
| 5949691 | Logic circuit verification device to verify the logic circuit equivalence and a method therefor | Hitoshi Kurosaka, Naotaka Maeda | 1999-09-07 |