VT

Victor Torres

NS National Semiconductor: 8 patents #229 of 2,238Top 15%
GE: 7 patents #4,929 of 36,430Top 15%
Dow Corning: 2 patents #658 of 1,768Top 40%
DS Dow Silicones: 1 patents #322 of 722Top 45%
Overall (All Time): #217,940 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11986588 Electronic system Benjamin Jung 2024-05-21
11764257 Systems and methods for junction termination of wide band gap super-junction power devices Stephen Daley Arthur, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov 2023-09-19
11271076 Systems and methods for junction termination in semiconductor devices Stephen Daley Arthur, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov 2022-03-08
11245003 Systems and methods for junction termination of wide band gap super-junction power devices Stephen Daley Arthur, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov 2022-02-08
10969409 Miniaturized current sensors 2021-04-06
10741551 Integrated vertical and lateral semiconductor devices 2020-08-11
10354871 Sputtering system and method for forming a metal layer on a semiconductor device Stacey Joy Kennerly, David Alan Lilienfeld, Robert Dwayne Gossman, Gregory Dudoff 2019-07-16
10014388 Transient voltage suppression devices with symmetric breakdown characteristics Reza Ghandi, David Alan Lilienfeld, Avinash Srikrishnan Kashyap, Alexander Viktorovich Bolotnikov 2018-07-03
10002760 Method for manufacturing SiC wafer fit for integration with power device manufacturing technology Darren Hansen, Mark Loboda, Ian Manning, Kevin Moeggenborg, Stephan Mueller +3 more 2018-06-19
9279192 Method for manufacturing SiC wafer fit for integration with power device manufacturing technology Darren Hansen, Mark Loboda, Ian Manning, Kevin Moeggenborg, Stephan Mueller +3 more 2016-03-08
8765091 Method to manufacture large uniform ingots of silicon carbide by sublimation/condensation processes Mark Loboda, Seung Ho Park 2014-07-01
7960240 System and method for providing a dual via architecture for thin film resistors Rodney Hill, Michael Burger, Terry Lines 2011-06-14
7808048 System and method for providing a buried thin film resistor having end caps defined by a dielectric mask Rodney Hill, William M. Coppock, Richard W. Foote, Terry Lines, Tom Bold 2010-10-05
7585775 System and method for faceting a masking layer in a plasma etch to slope a feature edge Thomas Bold, Rodney Hill 2009-09-08
7456097 System and method for faceting via top corners to improve metal fill Rodney Hill, Richard W. Foote 2008-11-25
7410879 System and method for providing a dual via architecture for thin film resistors Rodney Hill, Michael Burger, Terry Lines 2008-08-12
7332403 System and method for providing a buried thin film resistor having end caps defined by a dielectric mask Rodney Hill, William M. Coppock, Richard W. Foote, Terry Lines, Tom Bold 2008-02-19
7172973 System and method for selectively modifying a wet etch rate in a large area Richard W. Foote, William M. Coppock, Terry Lines 2007-02-06
7115500 System and method for providing a dry-wet-dry etch procedure to create a sidewall profile of a via 2006-10-03
6306675 Method for forming a low-defect epitaxial layer in the fabrication of semiconductor devices Ignatius S. T. Tsong, David J. Smith, John Edwards, R. Bruce Doak 2001-10-23