| 6771087 |
System and method for testing integrated circuit modules |
Abraham Mizrahi |
2004-08-03 |
| 5872960 |
Integrated circuit having CPU core operable for switching between two independent asynchronous clock sources of different frequencies while the CPU continues executing instructions |
Gideon Intrater, Yachin Afek |
1999-02-16 |
| 5649208 |
Mechanism for handling non-maskable interrupt requests received from different sources |
Gideon Intrater, Meir Tsadik |
1997-07-15 |
| 5638306 |
Testing hooks for testing an integrated data processing system |
Gideon Intrater, Alberto Sandbank |
1997-06-10 |
| 5613149 |
Integrated data processing system utilizing successive approximation analog to digital conversion and PWM for parallel disconnect |
Yachin Afek, Gideon Intrater |
1997-03-18 |
| 5603017 |
Parallel integrated circuit having DSP module and CPU core operable for switching between two independent asynchronous clock sources while the system continues executing instructions |
Gideon Intrater, Yachin Afek |
1997-02-11 |
| 5592677 |
Integrated data processing system including CPU core and parallel, independently operating DSP module |
Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony +14 more |
1997-01-07 |
| 5590357 |
Integrated CPU core and parallel, independently operating DSP module and time-critical core priority scheme |
Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony +14 more |
1996-12-31 |
| 5491828 |
Integrated data processing system having CPU core and parallel independently operating DSP module utilizing successive approximation analog to digital and PWM for parallel disconnect |
Gideon Intrater, Yachin Afek |
1996-02-13 |
| 5249286 |
Selectively locking memory locations within a microprocessor's on-chip cache |
Donald B. Alpert, Gideon Intrater, Reuven Marko, Alon Shacham |
1993-09-28 |