| 5623686 |
Non-volatile memory control and data loading architecture for multiple chip processor |
Christopher Michael Hall, William E. Miller, David W. Weinrich, Robert M. Salter, III, Richard E. Crippen |
1997-04-22 |
| 5613144 |
Serial register multi-input multiplexing architecture for multiple chip processor |
Christopher Michael Hall, David W. Weinrich |
1997-03-18 |
| 5606710 |
Multiple chip package processor having feed through paths on one die |
Christopher Michael Hall, William E. Miller, David W. Weinrich, Robert M. Salter, III, Richard E. Crippen |
1997-02-25 |
| 5598573 |
Multiple chip processor architecture with reset intercept circuit |
Christopher Michael Hall, David W. Weinrich, Robert M. Salter, III |
1997-01-28 |
| 5581779 |
Multiple chip processor architecture with memory interface control register for in-system programming |
Christopher Michael Hall, William E. Miller, David W. Weinrich, Robert M. Salter, III, Richard E. Crippen |
1996-12-03 |
| 5566344 |
In-system programming architecture for a multiple chip processor |
Christopher Michael Hall, William E. Miller, David W. Weinrich, Richard E. Crippen, Robert M. Salter, III |
1996-10-15 |
| 5319588 |
Signed overflow sticky bits |
Ralph Haines, D. Kevin Covey, Thomas W. S. Thomson |
1994-06-07 |
| 5311458 |
CPU with integrated multiply/accumulate unit |
Ralph Haines, D. Kevin Covey, Thomas W. S. Thomson |
1994-05-10 |
| 5218564 |
Layout efficient 32-bit shifter/register with 16-bit interface |
Ralph Haines, D. Kevin Covey, Thomas W. S. Thomson |
1993-06-08 |