Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8530306 | Method of forming a slit recess channel gate | Yi-Nan Chen, Hsien-Wen Liu | 2013-09-10 |
| 8525262 | Transistor with buried fins | Yi-Nan Chen, Hsien-Wen Liu | 2013-09-03 |
| 8501566 | Method for fabricating a recessed channel access transistor device | Chung-Yen Chou, Hsin-Jung Ho | 2013-08-06 |
| 8415729 | Power device with trenched gate structure and method of fabricating the same | Yi-Nan Chen, Hsien-Wen Liu | 2013-04-09 |
| 8343829 | Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same | Jer-Chyi Wang, Chung-Yuan Lee, Jeng-Ping Lin | 2013-01-01 |
| 7994559 | Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same | Jer-Chyi Wang, Chung-Yuan Lee, Jeng-Ping Lin | 2011-08-09 |
| 7091545 | Memory device and fabrication method thereof | Chien-Chang Huang, Chin-Ling Huang, Bo Ching Jiang, Yu-Wei Ting | 2006-08-15 |
| 7078315 | Method for eliminating inverse narrow width effects in the fabrication of DRAM device | Ming-Cheng Chang, Yinan Chen | 2006-07-18 |
| 6919245 | Dynamic random access memory cell layout and fabrication method thereof | Ming-Cheng Chang, Yi-Nan Chen, Jeng-Ping Lin | 2005-07-19 |
| 6875654 | Memory device and fabrication method thereof | Chien-Chang Huang, Chin-Ling Huang, Bo Ching Jiang, Yu-Wei Ting | 2005-04-05 |
| 6872619 | Semiconductor device having trench top isolation layer and method for forming the same | Yi-Nan Chen, Feng Lin | 2005-03-29 |