Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6657918 | Delayed locked loop implementation in a synchronous dynamic random access memory | Richard C. Foss, Peter B. Gillingham | 2003-12-02 |
| 6657919 | Delayed locked loop implementation in a synchronous dynamic random access memory | Richard C. Foss, Peter B. Gillingham | 2003-12-02 |
| 6538911 | Content addressable memory with block select for power management | G. F. Randall Gibson, Jason Edward Podaima | 2003-03-25 |
| 6327318 | Process, voltage, temperature independent switched delay compensation scheme | Gurpreet Bhullar | 2001-12-04 |
| 6314052 | Delayed locked loop implementation in a synchronous dynamic random access memory | Richard C. Foss, Peter B. Gillingham | 2001-11-06 |
| 6205083 | Delayed locked loop implementation in a synchronous dynamic random access memory | Richard C. Foss, Peter B. Gillingham | 2001-03-20 |
| 6067272 | Delayed locked loop implementation in a synchronous dynamic random access memory | Richard C. Foss, Peter B. Gillingham | 2000-05-23 |
| 5973552 | Power savings technique in solid state integrated circuits | — | 1999-10-26 |
| 5796673 | Delay locked loop implementation in a synchronous dynamic random access memory | Richard C. Foss, Peter B. Gillingham | 1998-08-18 |
| 5729160 | Self-timed circuit control device and method | — | 1998-03-17 |
| 5686848 | Power-up/power-down reset circuit for low voltage interval | Ian Mes | 1997-11-11 |
| 5642068 | Clock period dependent pulse generator | Tomasz Wojcicki | 1997-06-24 |
| 5416743 | Databus architecture for accelerated column access in RAM | Francis Larochelle | 1995-05-16 |
| 5402388 | Variable latency scheme for synchronous memory | Tomasz Wojcicki, Francis Larochelle | 1995-03-28 |