Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7983112 | Semiconductor device which transmits or receives a signal to or from an external memory by a DDR system | Masaru Haraguchi | 2011-07-19 |
| 7724606 | Interface circuit | Masaru Haraguchi, Yoshikazu Morooka, Hiroshi Kinoshita | 2010-05-25 |
| 7535251 | Semiconductor device and impedance adjusting method thereof | Chikayoshi Morishima, Masaru Haraguchi, Yoshihiro Yamashita | 2009-05-19 |
| 6742149 | Apparatus for testing semiconductor integrated circuits | — | 2004-05-25 |
| 6571364 | Semiconductor integrated circuit device with fault analysis function | Hideshi Maeno | 2003-05-27 |
| 6397363 | Semiconductor integrated circuit device with test circuit | Hideshi Maeno | 2002-05-28 |
| 6286121 | Semiconductor device | Hideshi Maeno | 2001-09-04 |
| 6275963 | Test circuit and a redundancy circuit for an internal memory circuit | Hideshi Maeno | 2001-08-14 |
| 5960008 | Test circuit | Hideshi Maeno | 1999-09-28 |
| 5946247 | Semiconductor memory testing device | Hideshi Maeno | 1999-08-31 |
| 5905737 | Test circuit | Hideshi Maeno | 1999-05-18 |
| 5903579 | Scan path forming circuit | Hideshi Maeno | 1999-05-11 |
| 5815512 | Semiconductor memory testing device | Hideshi Maeno | 1998-09-29 |
| 5724367 | Semiconductor memory device having scan path for testing | Hideshi Maeno | 1998-03-03 |
| 5703818 | Test circuit | — | 1997-12-30 |
| 5636225 | Memory test circuit | — | 1997-06-03 |