Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7139208 | Refresh-free dynamic semiconductor memory device | Kazutami Arimoto, Hiroki Shimano, Takeshi Fujino | 2006-11-21 |
| 7132850 | Semiconductor integrated circuit and circuit design apparatus | Takenobu Iwao | 2006-11-07 |
| 7003622 | Semiconductor memory | Hirofumi Shinohara, Yoshiki Tsujihashi | 2006-02-21 |
| 6934918 | IP (Intellectual Property) generating system | Kumiko Tsujihashi | 2005-08-23 |
| 6925022 | Refresh-free dynamic semiconductor memory device | Kazutami Arimoto, Hiroki Shimano, Takeshi Fujino | 2005-08-02 |
| 6820578 | Valve timing control device | Yoji Kanada, Osamu Komazawa | 2004-11-23 |
| 6755014 | NOx cleaning apparatus and NOx cleaning method for internal combustion engine | Kenji Kawai, Yoshinori Takahashi, Shinichi Saito, Toru Kawatani, Yoshinaka Takeda +3 more | 2004-06-29 |
| 6666019 | Exhaust emission control system of internal combustion engine | Toru Kawatani, Kihoko Kaita, Shinichi Saito, Junya Watanabe, Kenji Kawai +2 more | 2003-12-23 |
| 6634170 | Exhaust emission control system of internal combustion engine | Satoshi Hiranuma, Kihoko Kaita, Shinichi Saito, Junya Watanabe, Kenji Kawai +2 more | 2003-10-21 |
| 6539511 | Semiconductor integrated circuit devices with test circuit | — | 2003-03-25 |
| 6449204 | DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL SCHEME IN A NORMAL MODE TO A ONE BIT/TWO CELL SCHEME IN A TWIN-CELL MODE FOR LENGTHENING A REFRESH INTERVAL | Kazutami Arimoto, Hiroki Shimano, Takeshi Fujino | 2002-09-10 |
| 6259639 | Semiconductor integrated circuit device capable of repairing defective parts in a large-scale memory | — | 2001-07-10 |
| 5970096 | Synchronous serial transfer apparatus and synchronous serial transfer method | Hideki Yahiro, Kouji Hirano | 1999-10-19 |
| 5911039 | Integrated circuit device comprising a plurality of functional modules each performing predetermined function | Kazuhiro Sakashita | 1999-06-08 |
| 5841791 | Bypass scan path and integrated circuit device using the same | — | 1998-11-24 |
| 5715171 | Logical synthesizing device, logical synthesizing method, and semiconductor integrated circuit | Yasufumi Mori, Tatsunori Komoike | 1998-02-03 |
| 5703513 | Master-slave bistable latch with clock input control | Kazuhiro Sakashita | 1997-12-30 |
| 5646422 | Semiconductor integrated circuit device | — | 1997-07-08 |
| 5633806 | Semiconductor integrated circuit and method of designing same | Terukazu Yusa, Kazuhiro Sakashita, Isao Takimoto, Tatsunori Komoike | 1997-05-27 |
| 5621694 | Semiconductor integrated device with an improved performance | Mamoru Sakugawa, Kazuhiro Sakashita | 1997-04-15 |
| 5493506 | Integrated circuit device and method of designing same | Kazuhiro Sakashita, Isao Takimoto, Terukazu Yusa, Tatsunori Komoike | 1996-02-20 |
| 5448575 | Bypass scan path and integrated circuit device using the same | — | 1995-09-05 |
| 5315182 | Semiconductor integrated circuit having annular power supply with plural lines | Kazuhiro Sakashita, Terukazu Yusa, Isao Takimoto, Tatsunori Komoike | 1994-05-24 |
| 5260949 | Scan path system and an integrated circuit device using the same | Kazuhiro Sakashita | 1993-11-09 |
| 5173870 | Transmission and latch circuit for logic signal | Kazuhiro Sukashita, Yoshiki Tsujzhushi | 1992-12-22 |