Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6744679 | Semiconductor memory device | Masaki Tsukude, Takafumi Takatsuka | 2004-06-01 |
| 6707735 | Semiconductor memory device | Ryu Makabe, Masaki Tsukude | 2004-03-16 |
| 6697910 | Semiconductor memory device having refresh circuit | Masaki Tsukude, Shinichi Kobayashi | 2004-02-24 |
| 6584013 | Semiconductor memory device having increased memory capacity while reducing mounting area and stand-by current | Minoru Senda, Shinichi Kobayashi, Masaki Tsukude, Tadayuki Shimizu | 2003-06-24 |
| 6577553 | Semiconductor memory device | Ryu Makabe, Masaki Tsukude, Shinichi Kobayashi | 2003-06-10 |
| 6556485 | Output buffer capable of adjusting current drivability and semiconductor integrated circuit device having the same | Tadayuki Shimizu, Masaki Tsukude | 2003-04-29 |
| 6507337 | Touch panel | Kazuhiro Noda, Shuji Furukawa, Kohtaro Tanimura | 2003-01-14 |
| 6493279 | Semiconductor device capable of simple measurement of oscillation frequency | Masaki Tsukude, Tadayuki Shimizu | 2002-12-10 |
| 6388857 | Semiconductor circuit device with improved surge resistance | Shigeki Ohbayashi | 2002-05-14 |
| 6301678 | Test circuit for reducing test time in semiconductor memory device having multiple data input/output terminals | Tomohisa Wada, Shigeki Ohbayashi | 2001-10-09 |
| 6294404 | Semiconductor integrated circuit having function of reducing a power consumption and semiconductor integrated circuit system comprising this semiconductor integrated circuit | — | 2001-09-25 |
| 6118154 | Input/output protection circuit having an SOI structure | Yasuo Yamaguchi, Yasuo Inoue, Toshiaki Iwamatsu | 2000-09-12 |
| 5966319 | Static memory device allowing correct data reading | — | 1999-10-12 |
| 5963470 | Static semiconductor memory cell with improved data retention stability | — | 1999-10-05 |
| 5946251 | Bit line equalize circuit of semiconductor memory device | Yutaka Arita | 1999-08-31 |
| 5864511 | Semiconductor memory device using cross-coupled load and precharge circuit for bit line pairs | — | 1999-01-26 |
| 5841961 | Semiconductor memory device including a tag memory | Kunihiko Kozaru, Tomohisa Wada | 1998-11-24 |
| 5793670 | Static semiconductor memory device including a bipolar transistor in a memory cell, semiconductor device including bipolar transistors and method of manufacturing bipolar transistors | Tomohisa Wada, Hiroki Honda | 1998-08-11 |
| 5764565 | Static type semiconductor memory device with two word lines for one row | Motomu Ukita, Yutaka Arita | 1998-06-09 |
| 5754480 | Semiconductor device including an output buffer circuit that can output data while establishing impedance matching with an external data transmission line | — | 1998-05-19 |
| 5734280 | Semiconductor integrated circuit device having power on reset circuit | — | 1998-03-31 |
| 5708599 | Semiconductor memory device capable of reducing power consumption | Kunihiko Kozaru | 1998-01-13 |
| 5602798 | Synchronous semiconductor memory device operable in a snooze mode | Shigeki Ohbayashi | 1997-02-11 |
| 5546352 | Semiconductor memory device having decoder | Tomohisa Wada | 1996-08-13 |
| 5317213 | Level converter with delay circuitry used to increase switching speed | Atsushi Ohba, Akira Hosogane | 1994-05-31 |