Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6646944 | Semiconductor memory device | Katsumi Dosaka | 2003-11-11 |
| 6636454 | Low-power consumption semiconductor memory device | Takeshi Fujino, Kazutami Arimoto | 2003-10-21 |
| 6608795 | Semiconductor device including memory with reduced current consumption | Kazutami Arimoto | 2003-08-19 |
| 6597599 | Semiconductor memory | Toshinori Morihara, Katsumi Dosaka, Kazutami Arimoto | 2003-07-22 |
| 6590511 | Retrievable memory capable of outputting a piece of data with respect to a plurality of results of retrieve | Isamu Hayashi, Takeshi Fujino, Hideyuki Noda | 2003-07-08 |
| 6573613 | Semiconductor memory device having cell plate electrodes allowing independent power supply for each redundant replacement unit | Kazutami Arimoto | 2003-06-03 |
| 6545926 | Antifuse address detecting circuit programmable by applying a high voltage and semiconductor integrated circuit device provided with the same | Tsukasa Ooishi, Hideto Hidaka, Shigeki Tomishima | 2003-04-08 |
| 6486493 | Semiconductor integrated circuit device having hierarchical test interface circuit | Kazutami Arimoto | 2002-11-26 |
| 6487105 | Test circuit for semiconductor integrated circuit which detects an abnormal contact resistance | Toshinori Morihara | 2002-11-26 |
| 6483139 | Semiconductor memory device formed on semiconductor substrate | Kazutami Arimoto | 2002-11-19 |
| 6477108 | Semiconductor device including memory with reduced current consumption | Kazutami Arimoto | 2002-11-05 |
| 6459113 | Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells | Toshinori Morihara, Kazutami Arimoto | 2002-10-01 |
| 6456560 | Semiconductor integrated circuit device with test interface circuit for performing test on embedded memory from outside | Kazutami Arimoto | 2002-09-24 |
| 6452859 | Dynamic semiconductor memory device superior in refresh characteristics | Katsumi Dosaka, Kazutami Arimoto | 2002-09-17 |
| 6449204 | DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL SCHEME IN A NORMAL MODE TO A ONE BIT/TWO CELL SCHEME IN A TWIN-CELL MODE FOR LENGTHENING A REFRESH INTERVAL | Kazutami Arimoto, Takeshi Fujino, Takeshi Hashizume | 2002-09-10 |
| 6429495 | Semiconductor device with address programming circuit | Tsukasa Ooishi, Shigeki Tomishima | 2002-08-06 |
| 6418075 | Semiconductor merged logic and memory capable of preventing an increase in an abnormal current during power-up | Kazutami Arimoto, Yasuhiro Ishizuka, Seizou Furubeppu, Hiroki Sugano | 2002-07-09 |
| 6414890 | Semiconductor memory device capable of reliably performing burn-in test at wafer level | Kazutami Arimoto | 2002-07-02 |
| 6404684 | Test interface circuit and semiconductor integrated circuit device including the same | Kazutami Arimoto | 2002-06-11 |
| 6400625 | Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester | Kazutami Arimoto, Katsumi Dosaka | 2002-06-04 |
| 6400628 | Semiconductor memory device | Katsumi Dosaka, Hiroki Sugano, Kazutami Arimoto | 2002-06-04 |
| 6388929 | Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same | Kazutami Arimoto | 2002-05-14 |
| 6377483 | Semiconductor memory device having improved memory cell and bit line pitch | Kazutami Arimoto, Toshinori Morihara | 2002-04-23 |
| 6331956 | Synchronous semiconductor memory device having redundant circuit of high repair efficiency and allowing high speed access | Tsukasa Ooishi, Shigeki Tomishima | 2001-12-18 |
| 6327195 | Boosted-voltage drive circuit operable with high reliability and semiconductor memory device employing the same | Shigeki Tomishima, Tsukasa Ooishi | 2001-12-04 |