Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6501858 | Image compression and expansion apparatus using a effectively modifiable quantization table | — | 2002-12-31 |
| 6134349 | Device and method for processing run-length encoded signals by using an address generator | — | 2000-10-17 |
| 6091856 | Picture encoding device for compressing picture data | Hisashi Waki | 2000-07-18 |
| 5991446 | Image conversion device | — | 1999-11-23 |
| 5905813 | Image coding apparatus for compressing image data | — | 1999-05-18 |
| 5729706 | Microcomputer with improved data processing and data transfer capabilities | — | 1998-03-17 |
| 5584010 | Direct memory access control device and method in a multiprocessor system accessing local and shared memory | Hiroyuki Kawai | 1996-12-10 |
| 5497340 | Apparatus and method for detecting an overflow when shifting N bits of data | Shinichi Uramoto | 1996-03-05 |
| 5357457 | Adder with carry look ahead circuit | — | 1994-10-18 |
| 5311142 | Amplifier circuit with gain that does not vary with power supply fluctuations | Hiroyuki Sugino | 1994-05-10 |
| 5204962 | Processor with preceding operation circuit connected to output of data register | Shinichi Uramoto | 1993-04-20 |
| 5136701 | Processing unit containing DMA controller having concurrent operation with processor wherein addresses and data are divided into two parts | Hiroyuki Kawai | 1992-08-04 |
| 5095527 | Array processor | Shin-ichi Uramoto | 1992-03-10 |
| 5068818 | Hardware implemented moving average processor | Shinichi Uramoto | 1991-11-26 |
| 5051610 | SR latch circuit | Hiroyuki Kawai | 1991-09-24 |
| 4961191 | Test circuit for logic circuits | Shin Nakagawa | 1990-10-02 |
| 4954978 | Priority order decomposing apparatus | Shinichi Nakagawa | 1990-09-04 |
| 4913557 | Intergrated logic circuit having testing function circuit formed integrally therewith | Hiroshi Segawa | 1990-04-03 |
| 4910734 | Intergrated circuit having testing function circuit and control circuit therefor | Hiroshi Segawa | 1990-03-20 |
| 4899304 | Overflow detection circuit | Kazuya Ishihara | 1990-02-06 |
| 4897808 | Adder capable of usual addition and reverse carry addition | Shin Nakagawa, Hiroyuki Kawai, Kazuya Ishihara | 1990-01-30 |