Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5930520 | Pipelining device in a parallel processing apparatus and an instruction supplying method therefor | — | 1999-07-27 |
| 5918065 | Microprocessor with reduced area coupling a register file with a plurality of functional units | — | 1999-06-29 |
| 5870040 | 8/9 Coding apparatus and method of same | — | 1999-02-09 |
| 5809294 | Parallel processing unit which processes branch instructions without decreased performance when a branch is taken | — | 1998-09-15 |
| 5771377 | System for speculatively executing instructions using multiple commit condition code storages with instructions selecting a particular storage | — | 1998-06-23 |
| 5761467 | System for committing execution results when branch conditions coincide with predetermined commit conditions specified in the instruction field | — | 1998-06-02 |
| 5684983 | Microprocessor executing multiple register transfer operations with a single instruction with derivation of destination register numbers from source register | — | 1997-11-04 |
| 5636353 | Superscalar processor with direct result bypass between execution units having comparators in execution units for comparing operand and result addresses and activating results bypassing | Chikako Ikenaga | 1997-06-03 |
| 5619730 | Pipelining device in a parallel processing apparatus and an instruction supplying method therefor | — | 1997-04-08 |
| 5537402 | ATM switch | Hiromi Notani | 1996-07-16 |
| 5522084 | Method and system for invalidating instructions utilizing validity and write delay flags in parallel processing apparatus | — | 1996-05-28 |
| 5508761 | Apparatus for reproducing a digital pattern from motion picture film, and the motion picture film | Etsuro Saito, Katsuichi Tachi, Kiyoshi Inatome, Tetsuro Makise, Yoshiyuki Suzuki | 1996-04-16 |
| 5504923 | Parallel processing with improved instruction misalignment detection | — | 1996-04-02 |
| 5497496 | Superscalar processor controlling fetching of instructions based upon number of empty instructions registers detected for each cycle | — | 1996-03-05 |
| 5396640 | Boosting method and apparatus in a parallel computer | Chikako Ikenaga | 1995-03-07 |
| 5388235 | Arithmetic and logic processor and operating method therefor | Chikako Ikenaga | 1995-02-07 |
| 5386528 | Address translator having a high speed data comparator | Hirohisa Machida | 1995-01-31 |
| 5276820 | Arithmetic and logic processor and operating method therefor | Chikako Ikenaga | 1994-01-04 |
| 5239661 | Hierarchical bus circuit having decoder generating local buses and devices select signals enabling switching elements to perform data transfer operations | Chikako Ikenaga | 1993-08-24 |
| 5233691 | Register window system for reducing the need for overflow-write by prewriting registers to memory during times without bus contention | Hirohisa Machida | 1993-08-03 |
| 5225720 | Semiconductor integrated circuit device | Harlifusa Kondoh | 1993-07-06 |
| 5093588 | Bus circuit of precharge type for semiconductor integrated circuit | Chikako Ikenaga | 1992-03-03 |
| 4968988 | Time interleaved analog-digital converter and a method for driving the same | Takahiro Miki | 1990-11-06 |
| 4933892 | Integrated circuit device for orthogonal transformation of two-dimensional discrete data and operating method thereof | Masao Nakaya | 1990-06-12 |
| 4918451 | A/D converter with prevention of comparator output discontinuities | Takahiro Miki | 1990-04-17 |