Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7956661 | Standard cell and semiconductor device | — | 2011-06-07 |
| 6637003 | Viterbi decoder and synchronism controlling method | Michiru Hori | 2003-10-21 |
| 6587504 | Adaptive equalizer and designing method thereof | Shuji Murakami, Hiroyuki Mizutani, Hiroshi Ochi | 2003-07-01 |
| 6442580 | Resampling method and resampler circuit | — | 2002-08-27 |
| 5875323 | Processor using implicit register addressing | — | 1999-02-23 |
| 5812845 | Method for generating an object code for a pipeline computer process to reduce swapping instruction set | — | 1998-09-22 |
| 5805490 | Associative memory circuit and TLB circuit | — | 1998-09-08 |
| 5603023 | Processor circuit for heapsorting | — | 1997-02-11 |
| 5511189 | Data sorting apparatus capable of detecting completion of data sorting early and sorting method therefor | — | 1996-04-23 |
| 5468977 | Standard cells interconnection structure including a modified standard cell | — | 1995-11-21 |
| 5457788 | Associative memory system for performing hit judgment on cache data | — | 1995-10-10 |
| 5426599 | Hardware implemented multiplier for performing multiplication of two digital data according to booth algorithm | — | 1995-06-20 |
| 5386528 | Address translator having a high speed data comparator | Hideki Ando | 1995-01-31 |
| 5339268 | Content addressable memory cell and content addressable memory circuit for implementing a least recently used algorithm | — | 1994-08-16 |
| 5323347 | Semiconductor memory device storing two types of binary number data and method of operating the same | — | 1994-06-21 |
| 5233691 | Register window system for reducing the need for overflow-write by prewriting registers to memory during times without bus contention | Hideki Ando | 1993-08-03 |
| 5130692 | Improved data comparator for comparing plural-bit data at higher speed | Hideaki Ando | 1992-07-14 |
| 5048010 | Communication control processor | Takeo Nakabayashi | 1991-09-10 |
| 4963862 | Terminal equipment identifier control circuit | Takeo Nakabayashi | 1990-10-16 |
| 4943965 | Digital signal decoding method and circuit therefor | Takeo Nakabayashi | 1990-07-24 |
| 4827157 | Periodic signal generator circuit | Takeo Nakabayashi | 1989-05-02 |
| 4821225 | Arithmetic and logic unit with prior state dependent logic operations | Hideki Ando | 1989-04-11 |
| 4811267 | Digital signal processor with addressable and shifting memory | Hideki Ando, Harufusa Kondo | 1989-03-07 |