| 11226820 |
Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch |
Robert Gelinas, W. Patrick Hays, William J. Dally |
2022-01-18 |
| 9519507 |
Executing an instruction of currently active thread before context switch upon receiving inactive context ID to be activated |
Robert Gelinas, W. Patrick Hays, William J. Dally |
2016-12-13 |
| 9047093 |
Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities |
Robert Gelinas, W. Patrick Hays, William J. Dally |
2015-06-02 |
| 8209522 |
System and method for extracting fields from packets having fields spread over more than one register |
Robert Gelinas, W. Patrick Hays |
2012-06-26 |
| 7895423 |
Method for extracting fields from packets having fields spread over more than one register |
Robert Gelinas, W. Patrick Hays |
2011-02-22 |
| 7581091 |
System and method for extracting fields from packets having fields spread over more than one register |
Robert Gelinas, Patrick William Hays |
2009-08-25 |
| 7529915 |
Context switching processor with multiple context control register sets including write address register identifying destination register for waiting context to store returned data from external source |
Robert Gelinas, W. Patrick Hays, William J. Dally |
2009-05-05 |
| 7401205 |
High performance RISC instruction set digital signal processor having circular buffer and looping controls |
William J. Dally, W. Patrick Hays, Robert Gelinas, Sam Rosen, Staffan Ericsson |
2008-07-15 |
| 7162615 |
Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch |
Robert Gelinas, W. Patrick Hays, William J. Dally |
2007-01-09 |
| 7039060 |
System and method for extracting fields from packets having fields spread over more than one register |
Robert Gelinas, W. Patrick Hays |
2006-05-02 |