NG

Navneet Gupta

MO Minima Processor Oy: 8 patents #2 of 11Top 20%
CEA: 3 patents #1,381 of 7,956Top 20%
SN Stmicroelectronics International N.V.: 3 patents #160 of 696Top 25%
AA Aptiv Technologies Ag: 2 patents #314 of 863Top 40%
WT Western Digital Technologies: 1 patents #1,787 of 3,180Top 60%
IBM: 1 patents #44,794 of 70,183Top 65%
SS Stmicroelectronics Sa: 1 patents #938 of 1,676Top 60%
Overall (All Time): #232,072 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Showing 1–19 of 19 patents

Patent #TitleCo-InventorsDate
12182612 Method, arrangement, and computer program product for organizing the excitation of processing paths for testing a microelectric circuit Lauri Koskinen, Risto Anttila, Samuli Tuoriniemi 2024-12-31
12137515 Electromagnetic interference shielding and thermal management systems and methods for automotive radar applications Scott D. Brandenburg, David W. Zimmerman 2024-11-05
12113530 Microelectronic circuit capable of selectively activating processing paths, and a method for activating processing paths in a microelectronic circuit 2024-10-08
12085611 Applications of adaptive microelectronic circuits that are designed for testability Lauri Koskinen, Jesse Simonsson 2024-09-10
12032428 Asynchronous FIFO for power-domain crossing 2024-07-09
11953970 System with microelectronic circuit, and a method for controlling the operation of a microelectronic circuit Matthew Turnquist, Lauri Koskinen, Tuomas HOLLMAN 2024-04-09
11929746 Method and arrangement for protecting a digital circuit against time errors 2024-03-12
11894848 Register circuit with detection of data events, and method for detecting data events in a register circuit Lauri Koskinen 2024-02-06
11825593 Through board via heat sink Kesav Kumar Sridharan, Scott D. Brandenburg 2023-11-21
11699012 Coverage based microelectronic circuit, and method for providing a design of a microelectronic circuit 2023-07-11
11558039 Method and arrangement for ensuring valid data at a second stage of a digital register circuit 2023-01-17
10110203 Tri-state inverter, D latch and master-slave flip-flop comprising TFETs Adam Makosiej, Costin Anghel, Amara Amara 2018-10-23
10079056 SRAM memory bit cell comprising n-TFET and p-TFET Adam Makosiej, Costin Anghel, Amara Amara 2018-09-18
9860066 Location control of cloud data stores Shawn L. Berger, Rick A. Hamilton, II, Shawn P. Mullen, Nithya Alagu Renganathan, Karen Mariela Siles 2018-01-02
9679649 Reconfigurable cam Adam Makosiej, Costin Anghel, Amara Amara, Olivier Thomas 2017-06-13
8737144 Memory architecture and design methodology with adaptive read Prashant Dubey, ShaileshKumar Pathak, Kaushik Saha, Ashish Kumar, R Sai Krishna 2014-05-27
8624623 Apparatus having error detection in sequential logic Prashant Dubey, Kaushik Saha, AtulKumar Kashyap 2014-01-07
8456197 Differential data sensing Prashant Dubey, Shailesh Kumar Pathak, Kaushik Saha, Gagandeep Sachdev 2013-06-04
7944241 Circuit for glitchless switching between asynchronous clocks Vivek Sharma 2011-05-17