Issued Patents All Time
Showing 26–50 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6954400 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2005-10-11 |
| 6914813 | Segmented non-volatile memory array with multiple sources having improved source line decode circuitry | Christophe J. Chevallier | 2005-07-05 |
| 6856571 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2005-02-15 |
| 6842380 | Method and apparatus for erasing memory | Tz-Yi Liu | 2005-01-11 |
| 6809964 | Nonvolatile semiconductor memory device capable of transferring data internally without using an external bus | Anthony Moschopoulos | 2004-10-26 |
| 6809987 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2004-10-26 |
| 6798694 | Method for reducing drain disturb in programming | Andrei Mihnea | 2004-09-28 |
| 6760267 | Segmented non-volatile memory array with multiple sources having improved source line decode circuitry | Christophe J. Chevallier | 2004-07-06 |
| 6567335 | Memory system having flexible bus structure and method | Robert Norman, Christophe J. Chevallier | 2003-05-20 |
| 6567302 | Method and apparatus for programming multi-state cells in a memory device | — | 2003-05-20 |
| 6519691 | Method of controlling a memory device by way of a system bus | Robert Norman, Christophe J. Chevallier | 2003-02-11 |
| 6515936 | Memory system having flexible bus structure and method | Robert Norman, Christophe J. Chevallier | 2003-02-04 |
| 6507885 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2003-01-14 |
| 6407941 | Segmented non-volatile memory array with multiple sources having improved source line decode circuitry | Christophe J. Chevallier | 2002-06-18 |
| 6396729 | Memory system having flexible bus structure and method | Robert Norman, Christophe J. Chevallier | 2002-05-28 |
| 6363454 | Memory system having flexible architecture and method | Robert Norman, Christophe J. Chevallier | 2002-03-26 |
| 6353571 | Memory system having flexible bus structure and method | Robert Norman, Christophe J. Chevallier | 2002-03-05 |
| 6320815 | Memory system having flexible bus structure and method | Robert Norman, Christophe J. Chevallier | 2001-11-20 |
| 6307425 | Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit | Christophe J. Chevallier | 2001-10-23 |
| 6278642 | Method and apparatus for limiting bitline current | Christophe J. Chevallier | 2001-08-21 |
| 6253277 | Memory system having flexible addressing and method using tag and data bus communication | Robert Norman, Christophe J. Chevallier | 2001-06-26 |
| 6233173 | Apparatus and method for selecting data bits read from a multistate memory | Christophe J. Chevallier | 2001-05-15 |
| 6212123 | Memory system having flexible bus structure and method | Robert Norman, Christophe J. Chevallier | 2001-04-03 |
| 6175891 | System and method for assigning addresses to memory devices | Robert Norman | 2001-01-16 |
| 6175937 | Apparatus and method for programming multistate memory device | Robert Norman, Christophe J. Chevallier | 2001-01-16 |