Issued Patents All Time
Showing 126–148 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5982697 | Method for initializing and reprogramming a control operation feature of a memory device | Brett Williams | 1999-11-09 |
| 5912860 | Synchronous DRAM memory with asynchronous column decode | — | 1999-06-15 |
| 5905909 | Memory device having circuitry for initializing and reprogramming a control operation feature | Brett Williams | 1999-05-18 |
| 5896551 | Initializing and reprogramming circuitry for state independent memory array burst operations control | Brett Williams | 1999-04-20 |
| 5887162 | Memory device having circuitry for initializing and reprogramming a control operation feature | Brett Williams | 1999-03-23 |
| 5841726 | Method for initializing and reprogramming a control operation feature of a memory device | Brett Williams | 1998-11-24 |
| 5812842 | Method for initializing and reprogramming a control operation feature of a memory device | Brett Williams | 1998-09-22 |
| 5757715 | Method for initializing and reprogramming a control operation feature of a memory device | Brett Williams | 1998-05-26 |
| 5751656 | Synchronous DRAM memory with asynchronous column decode | — | 1998-05-12 |
| 5719817 | Memory array using selective device activation | — | 1998-02-17 |
| 5717639 | Memory device having circuitry for initializing and reprogramming a control operation feature | Brett Williams | 1998-02-10 |
| 5666321 | Synchronous DRAM memory with asynchronous column decode | — | 1997-09-09 |
| 5636173 | Auto-precharge during bank selection | — | 1997-06-03 |
| 5600605 | Auto-activate on synchronous dynamic random access memory | — | 1997-02-04 |
| 5566122 | Memory array using selective device activation | — | 1996-10-15 |
| 5544124 | Optimization circuitry and control for a synchronous memory device with programmable latency period | Paul S. Zagar | 1996-08-06 |
| 5457659 | Programmable dynamic random access memory (DRAM) | — | 1995-10-10 |
| 5414670 | Low power memory array using selective device activation | — | 1995-05-09 |
| 5335201 | Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs | Terry R. Walther | 1994-08-02 |
| 5257233 | Low power memory module using restricted RAM activation | — | 1993-10-26 |
| 5229970 | Circuit for synchronizing refresh cycles in self-refreshing drams having timing circuit shutdown | Terry R. Lee, Terry R. Walther | 1993-07-20 |
| 5229969 | Method for synchronizing refresh cycles in self-refreshing DRAMs having timing circuit shutdown | Terry R. Lee, Terry R. Walther | 1993-07-20 |
| 5208779 | Circuit for providing synchronous refresh cycles in self-refreshing interruptable DRAMs | Terry R. Walther | 1993-05-04 |