| 11340908 |
Reducing data hazards in pipelined processors to provide high processor utilization |
Alan T. Wootton, James Peterson |
2022-05-24 |
| 10776127 |
Reducing data hazards in pipelined processors to provide high processor utilization |
Alan T. Wootton, James Peterson |
2020-09-15 |
| 10114647 |
Reducing data hazards in pipelined processors to provide high processor utilization |
Alan T. Wootton, James Peterson |
2018-10-30 |
| 9161028 |
Image sensors with dark pixels for real-time verification of imaging systems |
Johannes Solhusvik |
2015-10-13 |
| 8730330 |
Image sensors with dark pixels for real-time verification of imaging systems |
Johannes Solhusvik |
2014-05-20 |
| 8711238 |
Systems and methods for synchronizing and controlling multiple image sensors |
Elaine W. Jin |
2014-04-29 |
| 8612728 |
Reducing data hazards in pipelined processors to provide high processor utilization |
Alan T. Wootton, James Peterson |
2013-12-17 |
| 8205017 |
Systems and methods for addressing and synchronizing multiple devices |
Ian Parr |
2012-06-19 |
| 8179460 |
System, method, and apparatus for variable rate pixel data transfer and storage |
Anthony Huggett, Graham Kirsch, Michael Lockey |
2012-05-15 |
| 7734899 |
Reducing data hazards in pipelined processors to provide high processor utilization |
Alan T. Wootton, James Peterson |
2010-06-08 |
| 7505317 |
Method, apparatus, and system for providing initial state random access memory |
David J. Warner |
2009-03-17 |
| 7200738 |
Reducing data hazards in pipelined processors to provide high processor utilization |
Alan T. Wootton, James Peterson |
2007-04-03 |
| 6983360 |
Program loading mechanism through a single input data path |
James Peterson |
2006-01-03 |
| 6889289 |
Method of distributed caching |
Alan T. Wootton |
2005-05-03 |
| 6754772 |
Distributed cache |
Alan T. Wootton |
2004-06-22 |
| 5615382 |
Data transfer system for buffering and selectively manipulating the size of data blocks being transferred between a processor and a system bus of a computer system |
Vincent Gavin, Michael J. Seaman, Bipin Mistry |
1997-03-25 |
| 5485586 |
Queue based arbitration using a FIFO data structure |
David L. A. Brash, John M. Lenthall |
1996-01-16 |
| 5471632 |
System for transferring data between a processor and a system bus including a device which packs, unpacks, or buffers data blocks being transferred |
Vincent Gavin, Michael J. Seaman, Bipin Mistry |
1995-11-28 |
| 5404474 |
Apparatus and method for addressing a variable sized block of memory |
Stewart Frederick Bryant, Michael J. Seaman, John M. Lenthall |
1995-04-04 |
| 5386523 |
Addressing scheme for accessing a portion of a large memory space |
Michael J. Seaman, David L. A. Brash |
1995-01-31 |
| 5357619 |
Paged memory scheme |
Vincent Gavin, Robert J. Galuszka, John M. Lenthall, Bipin Mistry, Clinton Choi +1 more |
1994-10-18 |
| 5291529 |
Handshake synchronization system |
Paul L. Bruce, Robert J. Galuszka |
1994-03-01 |
| 5255375 |
High performance interface between an asynchronous bus and one or more processors or the like |
Paul L. Bruce, Robert J. Galuszka |
1993-10-19 |
| 5202999 |
Access request prioritization and summary device |
John M. Lenthall, Helen C. McGreal, Michael J. Seaman |
1993-04-13 |
