JS

John Smythe

Micron: 129 patents #98 of 6,345Top 2%
ZI Zilog: 7 patents #8 of 150Top 6%
📍 Boise, ID: #43 of 3,546 inventorsTop 2%
🗺 Idaho: #58 of 8,810 inventorsTop 1%
Overall (All Time): #7,249 of 4,157,543Top 1%
139
Patents All Time

Issued Patents All Time

Showing 126–139 of 139 patents

Patent #TitleCo-InventorsDate
7479440 Method of forming an isolation structure that includes forming a silicon layer at a base of the recess William Budge 2009-01-20
7439157 Isolation trenches for memory devices Zailong Bian, Janos Fucsko, Michael P. Violette 2008-10-21
7273796 Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry Li Li, Janos Fucsko 2007-09-25
7271464 Liner for shallow trench isolation Jigish Trivedi, Robert D. Patraw, Kevin L. Beaman 2007-09-18
7271463 Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base William Budge 2007-09-18
7262135 Methods of forming layers 2007-08-28
7112513 Sub-micron space liner and densification process Jigish Trivedi 2006-09-26
6849510 Non-oxidizing spacer densification method for manufacturing semiconductor devices Brett D. Lowe, Timothy K. Carns 2005-02-01
6642112 Non-oxidizing spacer densification method for manufacturing semiconductor devices Brett D. Lowe, Timothy K. Carns 2003-11-04
6573141 In-situ etch and pre-clean for high quality thin oxides Bernice L. Kickel 2003-06-03
6436195 Method of fabricating a MOS device John E. Berg 2002-08-20
6190973 Method of fabricating a high quality thin oxide John E. Berg, Bernice L. Kickel 2001-02-20
6165846 Method of eliminating gate leakage in nitrogen annealed oxides Timothy K. Carns, John A. Ransom, Bernice L. Kickel, John E. Berg 2000-12-26
6156653 Method of fabricating a MOS device John E. Berg 2000-12-05