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Multiple data channel memory module architecture |
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Multiple data channel memory module architecture |
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| 9824010 |
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2017-11-21 |
| 9721660 |
Configurable volatile memory without a dedicated power source for detecting a data save trigger condition |
Bryan Kelly, Sriram Govindan, John J. Siegler, Badriddine Khessib, Mark Andrew Shaw |
2017-08-01 |
| 9558848 |
Testing storage device power circuitry |
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2017-01-31 |
| 9449659 |
Multiple data channel memory module architecture |
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Tony M. Brewer, Terrell Magee |
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James H. Hess, David Maciorowski, Edward A. Cross |
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Cable shield termination system using clamps and ferrules |
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Farrukh S. Syed, Brent Boudreaux, Eric C. Peterson, Richard A. Schumacher, Martha Geoghegan PETERSON |
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Controlling SDRAM memory by using truncated burst read-modify-write memory operations |
Donald H. Friedberg |
1999-10-26 |
| 5754557 |
Method for refreshing a memory, controlled by a memory controller in a computer system, in a self-refresh mode while scanning the memory controller |
— |
1998-05-19 |
