Issued Patents All Time
Showing 476–500 of 522 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6046615 | Level detection circuit | Christophe J. Chevallier, Michael S. Briner | 2000-04-04 |
| 6028798 | Low voltage test mode operation enable scheme with hardware safeguard | — | 2000-02-22 |
| 6014332 | Flash memory with adjustable write operation timing | — | 2000-01-11 |
| 5959485 | Controllable one-shot circuit and method for controlling operation of memory circuit using same | — | 1999-09-28 |
| 5956277 | Circuit and method for performing tests on memory array cells using external sense amplifier reference current | — | 1999-09-21 |
| 5956272 | Programming pulse with varying amplitude | — | 1999-09-21 |
| 5950145 | Low voltage test mode operation enable scheme with hardware safeguard | — | 1999-09-07 |
| 5943263 | Apparatus and method for programming voltage protection in a non-volatile memory system | — | 1999-08-24 |
| 5933434 | Memory system having internal state monitoring circuit | — | 1999-08-03 |
| 5930188 | Memory circuit for performing threshold voltage tests on cells of a memory array | — | 1999-07-27 |
| 5930168 | Flash memory with adjustable write operation timing | — | 1999-07-27 |
| 5900741 | CMOS buffer having stable threshold voltage | — | 1999-05-04 |
| 5901108 | Apparatus for externally timing high voltage cycles of non-volatile memory system | — | 1999-05-04 |
| 5880996 | Memory system having non-volatile data storage structure for memory control parameters and method | — | 1999-03-09 |
| 5864499 | Non-volatile data storage unit and method of controlling same | Michael S. Briner | 1999-01-26 |
| 5864569 | Method and apparatus for performing error correction on data read from a multistate memory | — | 1999-01-26 |
| 5825782 | Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns | — | 1998-10-20 |
| 5825700 | Low voltage test mode operation enable scheme with hardware safeguard | — | 1998-10-20 |
| 5808946 | Parallel processing redundancy scheme for faster access times and lower die area | — | 1998-09-15 |
| 5801985 | Memory system having programmable control parameters | Darrell Rinerson, Christophe J. Chevallier, Michael S. Briner | 1998-09-01 |
| 5793775 | Low voltage test mode operation enable scheme with hardware safeguard | — | 1998-08-11 |
| 5790459 | Memory circuit for performing threshold voltage tests on cells of a memory array | — | 1998-08-04 |
| 5774401 | Data input/output circuit for performing high speed memory data read operation | — | 1998-06-30 |
| 5767711 | Level detection circuit and method | Christophe J. Chevallier, Michael S. Briner | 1998-06-16 |
| 5761130 | Data input/output circuit for performing high speed memory data read operation | — | 1998-06-02 |