Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9122570 | Data pattern generation for I/O training and characterization | Timothy M. Hollis, Jeffrey P. Wright, Kang-Yong Kim | 2015-09-01 |
| 7664999 | Real time testing using on die termination (ODT) circuit | — | 2010-02-16 |
| 7574634 | Real time testing using on die termination (ODT) circuit | — | 2009-08-11 |
| 7274606 | Low power chip select (CS) latency option | — | 2007-09-25 |
| 7167401 | Low power chip select (CS) latency option | — | 2007-01-23 |
| 6788126 | Semiconductor buffer circuit with a transition delay circuit | — | 2004-09-07 |
| 6707136 | Multi-layer lead frame for a semiconductor device | — | 2004-03-16 |
| 6707312 | Pseudo variable resistor for tester platform | — | 2004-03-16 |
| 6515353 | Multi-layer lead frame for a semiconductor device | — | 2003-02-04 |
| 6515529 | Semiconductor buffer circuit with a transition delay circuit | — | 2003-02-04 |
| 6438043 | Adjustable I/O timing from externally applied voltage | Dean D. Gans, Joseph T. Pawlowski | 2002-08-20 |
| 6307255 | Multi-layer lead frame for a semiconductor device | — | 2001-10-23 |
| 6278310 | Semiconductor buffer circuit with a transition delay circuit | — | 2001-08-21 |
| 6166576 | Method and apparatus for controlling timing of digital components | — | 2000-12-26 |
| 6154078 | Semiconductor buffer circuit with a transition delay circuit | — | 2000-11-28 |
| 6124630 | Multi-layer lead frame for a semiconductor device | — | 2000-09-26 |
| 6002623 | Semiconductor memory with test circuit | Phillip G. Wald | 1999-12-14 |
| 5965936 | Multi-layer lead frame for a semiconductor device | — | 1999-10-12 |
| 5892720 | Semiconductor memory with test circuit | Phillip G. Wald | 1999-04-06 |
| 5734198 | Multi-layer lead frame for a semiconductor device | — | 1998-03-31 |
| 5684809 | Semiconductor memory with test circuit | Phillip G. Wald | 1997-11-04 |