Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367148 | Variable execution time atomic operations | Tony M. Brewer | 2025-07-22 |
| 12321274 | Recall pending cache line eviction | Tony M. Brewer | 2025-06-03 |
| 12282800 | Thread replay to preserve state in a barrel processor | Chris Baronne, John Amelio | 2025-04-22 |
| 12190987 | Method for configuring multiple input-output channels | Tony M. Brewer | 2025-01-07 |
| 12135987 | Thread scheduling control and memory splitting in a barrel processor | Chris Baronne, John Amelio | 2024-11-05 |
| 12111770 | Silent cache line eviction | Tony M. Brewer | 2024-10-08 |
| 12111758 | Synchronized request handling at a memory device | Tony M. Brewer | 2024-10-08 |
| 12079516 | Host-preferred memory operation | Tony M. Brewer | 2024-09-03 |
| 12020064 | Rescheduling a failed memory request in a processor | Chris Baronne, John Amelio | 2024-06-25 |
| 12013788 | Evicting a cache line with pending control request | Tony M. Brewer | 2024-06-18 |
| 11960768 | Memory-side cache directory-based request queue | Tony M. Brewer | 2024-04-16 |
| 11960403 | Variable execution time atomic operations | Tony M. Brewer | 2024-04-16 |
| 11953989 | Low-latency register error correction | Chris Baronne | 2024-04-09 |
| 11940919 | Recall pending cache line eviction | Tony M. Brewer | 2024-03-26 |
| 11914516 | Memory side cache request handling | Tony M. Brewer | 2024-02-27 |
| 11868300 | Deferred communications over a synchronous interface | Tony M. Brewer | 2024-01-09 |
| 11734173 | Memory access bounds checking for a programmable atomic operator | Tony M. Brewer, Chris Baronne | 2023-08-22 |
| 11726914 | Bias control for a memory device | Bryan Hornung, Tony M. Brewer, David Patrick, Christopher Baronne | 2023-08-15 |
| 11722138 | Dynamic power and thermal loading in a chiplet-based system | Tony M. Brewer, David Patrick, Michael Grassi, Bryan Hornung | 2023-08-08 |
| 11698791 | On-demand programmable atomic kernel loading | Tony M. Brewer, Chris Baronne | 2023-07-11 |
| 11669486 | Initialization sequencing of chiplet I/O channels within a chiplet system | Tony M. Brewer | 2023-06-06 |
| 11669487 | Secondary device detection using a synchronous interface | Tony M. Brewer | 2023-06-06 |
| 11650876 | Payload parity protection for a synchronous interface | Tony M. Brewer | 2023-05-16 |
| 11614942 | Reuse in-flight register data in a processor | Christopher Baronne | 2023-03-28 |
| 11586443 | Thread-based processor halting | Christopher Baronne | 2023-02-21 |