Issued Patents All Time
Showing 51–75 of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7984207 | Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction | — | 2011-07-19 |
| 7826283 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Brian Johnson | 2010-11-02 |
| 7747933 | Method and apparatus for detecting communication errors on a bus | — | 2010-06-29 |
| 7636271 | User selectable banks for DRAM | — | 2009-12-22 |
| 7603493 | Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction | — | 2009-10-13 |
| 7596461 | Measurement of air quality in wireless networks | Brian D. Hart, Igal Gutkin, Sanjeev Hemantkumar Desal | 2009-09-29 |
| 7457978 | Adjustable byte lane offset for memory module to reduce skew | — | 2008-11-25 |
| 7450447 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Brian Johnson | 2008-11-11 |
| 7254067 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Brian Johnson | 2007-08-07 |
| 7215582 | Controlling multiple signal polarity in a semiconductor device | — | 2007-05-08 |
| 7203122 | User selectable banks for DRAM | — | 2007-04-10 |
| 7181401 | Methods for generating voice prompts using grammatical rules in a system proving TDM voice communications and VOIP communications | Scott K. Pickett | 2007-02-20 |
| 7177231 | Selectable clock input | Scott E. Schaefer | 2007-02-13 |
| 7177224 | Controlling multiple signal polarity in a semiconductor device | — | 2007-02-13 |
| 7149141 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Brian Johnson | 2006-12-12 |
| 7149824 | Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction | — | 2006-12-12 |
| 7120754 | Synchronous DRAM with selectable internal prefetch size | Kevin J. Ryan | 2006-10-10 |
| 7027337 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Brian Johnson | 2006-04-11 |
| 7009863 | Memory module with integrated bus termination | Dirgha Khatri, Dail Robert Cox | 2006-03-07 |
| 6990041 | Selectable clock input | Scott E. Schaefer | 2006-01-24 |
| 6981100 | Synchronous DRAM with selectable internal prefetch size | Kevin J. Ryan | 2005-12-27 |
| 6934199 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Brian Johnson | 2005-08-23 |
| 6895474 | Synchronous DRAM with selectable internal prefetch size | Kevin J. Ryan | 2005-05-17 |
| 6888719 | Methods and apparatuses for transferring heat from microelectronic device modules | Jeffery W. Janzen | 2005-05-03 |
| 6754129 | Memory module with integrated bus termination | Dirgha Khatri, Dail Robert Cox | 2004-06-22 |