Issued Patents All Time
Showing 51–75 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7626865 | Charge pump operation in a non-volatile memory device | — | 2009-12-01 |
| 7613070 | Interleaved input signal path for multiplexed input | — | 2009-11-03 |
| 7486566 | Methods, apparatus, and systems for flash memory bit line charging | — | 2009-02-03 |
| 7483334 | Interleaved input signal path for multiplexed input | — | 2009-01-27 |
| 7453737 | Program method with optimized voltage level for flash memory | — | 2008-11-18 |
| 7388789 | NAND memory device and programming methods | — | 2008-06-17 |
| 7359243 | Memory cell repair using fuse programming method in a flash memory device | — | 2008-04-15 |
| 7317647 | Noise suppression in memory device sensing | — | 2008-01-08 |
| 7289363 | Memory cell repair using fuse programming method in a flash memory device | — | 2007-10-30 |
| 7248499 | Layout for NAND flash memory array having reduced word line impedance | Ebrahim Abedifard | 2007-07-24 |
| 7239557 | Program method with optimized voltage level for flash memory | — | 2007-07-03 |
| 7227800 | Noise suppression in memory device sensing | — | 2007-06-05 |
| 7170783 | Layout for NAND flash memory array having reduced word line impedance | Ebrahim Abedifard | 2007-01-30 |
| 7079434 | Noise suppression in memory device sensing | — | 2006-07-18 |
| 7009910 | Semiconductor memory having a flexible dual-bank architecture with improved row decoding | — | 2006-03-07 |
| 6781914 | Flash memory having a flexible bank partition | — | 2004-08-24 |
| 6704241 | Memory architecture with vertical and horizontal row decoding | — | 2004-03-09 |
| 6590810 | Source biasing circuit for flash EEPROM | — | 2003-07-08 |
| 6510084 | Column decoder with increased immunity to high voltage breakdown | — | 2003-01-21 |
| 6021067 | Circuit of sensing a fuse cell in a flash memory | — | 2000-02-01 |
| 5852580 | Repair fuse circuit in a flash memory device | — | 1998-12-22 |
| 5784317 | Flash memory device using an operational circuit for bit-by-bit verifying of programmed data in memory cells and method of programming the same | — | 1998-07-21 |
| 5617354 | Sensing circuit to enhance sensing margin | Byoung Kwon Cha | 1997-04-01 |
| 5406519 | Real-only memory device incorporating storage memory array and security memory array coupled to comparator circuirtry | — | 1995-04-11 |
| 5373510 | Test circuit of input architecture of erasable and programmable logic device | — | 1994-12-13 |