Issued Patents All Time
Showing 51–64 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8274832 | Dynamic polarization for reducing stress induced leakage current | Luca Chiavarone, Mattia Robustelli | 2012-09-25 |
| 8169827 | NAND flash memory string apparatus and methods of operation thereof | Pietro Guzzi | 2012-05-01 |
| 7940568 | Dynamic polarization for reducing stress induced leakage current | Luca Chiavarone, Mattia Robustelli | 2011-05-10 |
| 7730383 | Structure and method for detecting errors in a multilevel memory device with improved programming granularity | — | 2010-06-01 |
| 7710778 | NAND flash memory with reduced programming disturbance | Silvia Beltrami | 2010-05-04 |
| 7678575 | Method for the detection of phosphine in cereals | Roberto Ranieri, Marco Silvestri, Michelangelo Pascale, Francesco Longobardi | 2010-03-16 |
| 7551465 | Reference cell layout with enhanced RTN immunity | Tecla Ghilardi, Paolo Tessariol, Giorgio Servalli, Alessandro Grossi, Emilio Camerlenghi | 2009-06-23 |
| 7535770 | Flash memory device with reduced drain stresses | Silvia Beltrami | 2009-05-19 |
| 7478292 | Structure and method for detecting errors in a multilevel memory device with improved programming granularity | — | 2009-01-13 |
| 7471571 | Method for programming a memory device suitable to minimize the lateral coupling effects between memory cells | Mauro Bonanomi | 2008-12-30 |
| 7110300 | Method of programming a multi-level, electrically programmable non-volatile semiconductor memory | — | 2006-09-19 |
| 6654287 | Method of re-programming an array of non-volatile memory cells, in particular of the nor architecture flash type, after an erase operation, and a corresponding memory device | — | 2003-11-25 |
| 6530058 | Method for correction of errors in a binary word stored in multilevel memory cells, not requiring additional cells | — | 2003-03-04 |
| 6519183 | Method and a circuit structure for modifying the threshold voltages of non-volatile memory cells | — | 2003-02-11 |