Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393429 | Atomic instruction set and architecture with bus arbitration locking | Robert G. Ellis, Stephen Bowling | 2025-08-19 |
| 12346722 | Systems and methods for managing interrupt priority levels | Howard Henry Schlunder, David Mickey | 2025-07-01 |
| 12093688 | Multibit shift instruction | David Mickey, Ashish Desai, Jason M. Sachs, Calum Wilkie | 2024-09-17 |
| 12001270 | Vector fetch bus error handling | David Mickey | 2024-06-04 |
| 10983931 | Central processing unit with enhanced instruction set | David Mickey, Bryan Kris, Calum Wilkie, Jason M. Sachs, Andreas Reiter | 2021-04-20 |
| 10802866 | Central processing unit with DSP engine and enhanced context switch capabilities | David Mickey | 2020-10-13 |
| 10776292 | Apparatus and method for protecting program memory for processing cores in a multi-core integrated circuit | David Mickey, Bryan Kris, Calum Wilkie, Jason M. Sachs, Andreas Reiter | 2020-09-15 |
| 10248521 | Run time ECC error injection scheme for hardware validation | Brant Ivey, Sankar Rangarajan | 2019-04-02 |
| 10120815 | Configurable mailbox data buffer apparatus | David Mickey, Bryan Kris | 2018-11-06 |
| 9858083 | Dual boot panel SWAP mechanism | Brant Ivey, Igor Wojewoda, David Mickey, Joseph Kanellopoulos | 2018-01-02 |
| 9619231 | Programmable CPU register hardware context swap mechanism | Bryan Kris, David Mickey, Joseph Kanellopoulos | 2017-04-11 |
| 8984198 | Data space arbiter | Ashish Desai | 2015-03-17 |
| 8856406 | Peripheral trigger generator | Bryan Kris | 2014-10-07 |
| 8688964 | Programmable exception processing latency | David Mickey | 2014-04-01 |
| 8645729 | External device power control during low power sleep mode without central processing unit intervention | Michael Simmons | 2014-02-04 |
| 8495125 | DSP engine with implicit mixed sign operands | Settu Duraisamy | 2013-07-23 |
| 7966480 | Register pointer trap to prevent errors due to an invalid pointer value in a register | — | 2011-06-21 |
| 7467178 | Dual mode arithmetic saturation processing | — | 2008-12-16 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection | — | 2007-07-10 |
| 7020788 | Reduced power option | — | 2006-03-28 |
| 7007172 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection | — | 2006-02-28 |
| 6976158 | Repeat instruction with interrupt | Joseph W. Triece | 2005-12-13 |
| 6952711 | Maximally negative signed fractional number multiplication | — | 2005-10-04 |
| 6934728 | Euclidean distance instructions | — | 2005-08-23 |
| 6728856 | Modified Harvard architecture processor having program memory space mapped to data memory space | James H. Grosbach, Joshua M. Conner | 2004-04-27 |