Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12346722 | Systems and methods for managing interrupt priority levels | Michael Catherwood, Howard Henry Schlunder | 2025-07-01 |
| 12093688 | Multibit shift instruction | Michael Catherwood, Ashish Desai, Jason M. Sachs, Calum Wilkie | 2024-09-17 |
| 12001270 | Vector fetch bus error handling | Michael Catherwood | 2024-06-04 |
| 10983931 | Central processing unit with enhanced instruction set | Michael Catherwood, Bryan Kris, Calum Wilkie, Jason M. Sachs, Andreas Reiter | 2021-04-20 |
| 10802866 | Central processing unit with DSP engine and enhanced context switch capabilities | Michael Catherwood | 2020-10-13 |
| 10776292 | Apparatus and method for protecting program memory for processing cores in a multi-core integrated circuit | Michael Catherwood, Bryan Kris, Calum Wilkie, Jason M. Sachs, Andreas Reiter | 2020-09-15 |
| 10120815 | Configurable mailbox data buffer apparatus | Michael Catherwood, Bryan Kris | 2018-11-06 |
| 9858083 | Dual boot panel SWAP mechanism | Michael Catherwood, Brant Ivey, Igor Wojewoda, Joseph Kanellopoulos | 2018-01-02 |
| 9619231 | Programmable CPU register hardware context swap mechanism | Michael Catherwood, Bryan Kris, Joseph Kanellopoulos | 2017-04-11 |
| 8688964 | Programmable exception processing latency | Michael Catherwood | 2014-04-01 |