Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9984193 | System to combat design-time vulnerability | Serge Leef, Ahmed A. Badran | 2018-05-29 |
| 9619598 | Input space reduction for verification test set generation | Clifton Alton Lyons, Jr., Kunal P. Ganeshpure | 2017-04-11 |
| 9135376 | Input space reduction for verification test set generation | Clifton Alton Lyons, Jr., Kunal P. Ganeshpure | 2015-09-15 |
| 8930878 | System to combat design-time vulnerability | Serge Leef, Ahmed A. Badran | 2015-01-06 |
| 7549100 | Dynamic verification traversal strategies | Clifton Alton Lyons, Jr. | 2009-06-16 |
| 7290193 | System verification using one or more automata | Clifton Alton Lyons, Jr. | 2007-10-30 |
| 7234093 | Resource management during system verification | — | 2007-06-19 |
| 7234094 | Automaton synchronization during system verification | Clifton Alton Lyons, Jr. | 2007-06-19 |