Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9619598 | Input space reduction for verification test set generation | Sudhir Kadkade, Kunal P. Ganeshpure | 2017-04-11 |
| 9135376 | Input space reduction for verification test set generation | Sudhir Kadkade, Kunal P. Ganeshpure | 2015-09-15 |
| 7549100 | Dynamic verification traversal strategies | Sudhir Kadkade | 2009-06-16 |
| 7290193 | System verification using one or more automata | Sudhir Kadkade | 2007-10-30 |
| 7234094 | Automaton synchronization during system verification | Sudhir Kadkade | 2007-06-19 |