Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6336087 | Method and apparatus for gate-level simulation of synthesized register transfer level design with source-level debugging | Alain Raynaud | 2002-01-01 |
| 6301553 | Method and apparatus for removing timing hazards in a circuit design | Frederic Emirian | 2001-10-09 |
| 6240376 | Method and apparatus for gate-level simulation of synthesized register transfer level designs with source-level debugging | Alain Raynaud | 2001-05-29 |
| 5831866 | Method and apparatus for removing timing hazards in a circuit design | Olivier LePape, Frederic Reblewski | 1998-11-03 |
| 5801955 | Method and apparatus for removing timing hazards in a circuit design | Olivier LePape, Frederic Reblewski | 1998-09-01 |