AR

Alain Raynaud

MG Mentor Graphics: 1 patents #345 of 698Top 50%
Overall (All Time): #2,209,363 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6336087 Method and apparatus for gate-level simulation of synthesized register transfer level design with source-level debugging Luc Burgun 2002-01-01
6240376 Method and apparatus for gate-level simulation of synthesized register transfer level designs with source-level debugging Luc Burgun 2001-05-29