Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10002833 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance | Ching-Chung Ko, Tao Cheng, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke | 2018-06-19 |
| 9698102 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance | Ching-Chung Ko, Tao Cheng, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke | 2017-07-04 |
| 9379059 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance | Ching-Chung Ko, Tao Cheng, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke | 2016-06-28 |
| 8661388 | Method of packing-based macro placement and semiconductor chip using the same | Tung-Chieh Chen, Ping Yu, Yao-Wen Chang, Fwu-Juh Huang | 2014-02-25 |
| 8120067 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance | Ching-Chung Ko, Tao Cheng, Dar-Shii Chou, Peng-Cheng Kao | 2012-02-21 |
| 8072004 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance | Ching-Chung Ko, Tao Cheng, Dar-Shii Chou, Peng-Cheng Kao | 2011-12-06 |
| 7821038 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance | Ching-Chung Ko, Tao Cheng, Dar-Shii Chou, Peng-Cheng Kao | 2010-10-26 |
| 6708312 | Method for multi-threshold voltage CMOS process optimization | Ming-Mao Chiang, Ching-Chang Shih, Chin-Cho Tsai, Kuo-Chung Huang | 2004-03-16 |