Issued Patents All Time
Showing 51–75 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10566348 | Tilted hemi-cylindrical 3D NAND array having bottom reference conductor | Hang-Ting Lue | 2020-02-18 |
| 10535673 | High-density flash memory device and method of manufacturing the same | Chih-Wei Hu, Hang-Ting Lue | 2020-01-14 |
| 10490498 | Three-dimensional semiconductor device with isolated dummy pattern | Min-Feng Hung, Chih-Wei Hu | 2019-11-26 |
| 10388720 | Capacitor with 3D NAND memory | Hang-Ting Lue | 2019-08-20 |
| 10340222 | Stair contact structure, manufacturing method of stair contact structure, and memory structure | Chih-Wei Hu | 2019-07-02 |
| 10068914 | Semiconductor structure and manufacturing method of the same | Yu-Wei Jiang | 2018-09-04 |
| 10014306 | Memory structure and manufacturing method for the same | Chih-Wei Hu | 2018-07-03 |
| 9947665 | Semiconductor structure having dielectric layer and conductive strip | Chih-Wei Hu | 2018-04-17 |
| 9761319 | Reading method for preventing read disturbance and memory using the same | Kuo-Pin Chang, Hang-Ting Lue | 2017-09-12 |
| 9748264 | Semiconductor structure and manufacturing method thereof | Yu-Wei Jiang | 2017-08-29 |
| 9741569 | Forming memory using doped oxide | Chih-Wei Hu | 2017-08-22 |
| 9721668 | 3D non-volatile memory array with sub-block erase architecture | Kuo-Pin Chang | 2017-08-01 |
| 9716137 | 3D capacitor with 3D memory | Chih-Wei Hu | 2017-07-25 |
| 9685408 | Contact pad structure and method for fabricating the same | Yu-Wei Jiang, Chia-Jung Chiou, Chih-Yao Lin | 2017-06-20 |
| 9679913 | Memory structure and method for manufacturing the same | Chih-Wei Hu | 2017-06-13 |
| 9627498 | Contact structure for thin film semiconductor | Jia-Rong Chiou, Yu-Wei Jiang | 2017-04-18 |
| 9576976 | Three dimensional memory device | Chih-Wei Hu | 2017-02-21 |
| 9536573 | 3D memory structure and method for manufacturing the same | Chih-Wei Hu | 2017-01-03 |
| 9490249 | Antenna effect discharge circuit and manufacturing method | Hang-Ting Lue | 2016-11-08 |
| 9478259 | 3D voltage switching transistors for 3D vertical gate memory array | Chih-Wei Hu, Lee-Yin Lin | 2016-10-25 |
| 9461064 | Multi-layer memory array and manufacturing method of the same | Chih-Wei Hu, Yen-Hao Shih | 2016-10-04 |
| 9461062 | Semiconductor device and manufacturing method thereof | Chih-Wei Hu | 2016-10-04 |
| 9412752 | Reference line and bit line structure for 3D memory | Chih-Wei Hu, Yu-Wei Jiang | 2016-08-09 |
| 9397209 | Semiconductor structure and manufacturing method of forming a large pattern and a plurality of fine gate lines located between the large patterns | Yen-Hao Shih | 2016-07-19 |
| 9330764 | Array fanout pass transistor structure | Lee-Yin Lin, Chih-Wei Hu, Chieh-Fang Chen | 2016-05-03 |