Issued Patents All Time
Showing 76–96 of 96 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7355903 | Semiconductor device including memory cells and current limiter | Chun-Hsiung Hung, Chuan-Ying Yu, Nai-Ping Kuo, Ching-Chung Lin, Kuen-Long Chang | 2008-04-08 |
| 7345917 | Non-volatile memory package and method of reading stored data from a non-volatile memory array | Chun-Hsiung Hung, Su-Chueh Lo | 2008-03-18 |
| 7315482 | Memory device with a plurality of reference cells on a bit line | Ching-Chung Lin, Nai-Ping Kuo | 2008-01-01 |
| 7289359 | Systems and methods for using a single reference cell in a dual bit flash memory | Nai-Ping Kuo, Ken-Hui Chen, Chun-Hsiung Hung | 2007-10-30 |
| 7236404 | Structures and methods for enhancing erase uniformity in an NROM array | Ching-Chung Lin, Ken-Hui Chen, Nai-Ping Kuo, Chun-Hsiung Hung, Wen-Yi Hsieh | 2007-06-26 |
| 7233530 | System and method for over erase reduction of nitride read only memory | Ching-Chung Lin, Nai-Ping Kuo | 2007-06-19 |
| 7180782 | Read source line compensation in a non-volatile memory | Chuan-Ying Yu, Nai-Ping Kuo, Ken-Hui Chen, Chun-Hsiung Hung | 2007-02-20 |
| 7002850 | System and method for over erase reduction of nitride read only memory | Ching-Chung Lin, Nai-Ping Kuo | 2006-02-21 |
| 6795350 | Circuit and method for tuning a reference bit line loading to a sense amplifier by optionally cutting a capacitive reference bit line | Kuo-Yu Liao, Chen-Hao Po, Chun-Hsiung Hung | 2004-09-21 |
| 6618848 | Method for designing circuit layout of non-neighboring metal bit lines to reduce coupling effect | Kuo-Yu Liao, Yung-Feng Lin, Chun-Hsiung Hung, Ho-Chun Liou | 2003-09-09 |
| 6608499 | Method for compensating a threshold voltage of a neighbor bit | Tseng-Yi Liu, Cheng-Jye Liu, Chia-Hsing Chen, Chun-Hsiung Hung | 2003-08-19 |
| 6496417 | Method and integrated circuit for bit line soft programming (BLISP) | Tzeng-Huei Shiau, Ray-Lin Wan, Yu-Shen Lin, Wen-Pin Lu, Tso-Ming Chang | 2002-12-17 |
| 6438039 | Erasing device and method for flash memory | Tseng-Yi Liu, Chun-Hsiung Hung | 2002-08-20 |
| 6421275 | Method for adjusting a reference current of a flash nitride read only memory (NROM) and device thereof | Nai-Ping Kuo, Kuo-Yu Liao, Chun-Hsiung Hung | 2002-07-16 |
| 6385097 | Method for tracking metal bit line coupling effect | Kuo-Yu Liao, Chun-Hsiung Hung, Ho-Chun Liou | 2002-05-07 |
| 6178132 | Non-volatile integrated circuit having read while write capability using one address register | Chun-Hsiung Hung, Kuo-Yu Liao, Ray-Lin Wan | 2001-01-23 |
| 6119226 | Memory supporting multiple address protocols | Tzeng-Huei Shiau, Tso-Ming Chang, Ray-Lin Wan, Fuchia Shone | 2000-09-12 |
| 6084446 | Power on reset circuit | Tzeng-Huei Shiau, Ray-Lin Wan | 2000-07-04 |
| 5818764 | Block-level wordline enablement to reduce negative wordline stress | Tom D. Yiu, I-Long Lee, Kuen-Long Chang, Tzeng-Huei Shiau, Chun-Hsiung Hung +1 more | 1998-10-06 |
| 5787039 | Low current floating gate programming with bit-by-bit verification | Tzeng-Huei Shiau, Yu-Shen Lin, Chung-Cheng Tsai, Jin-Lien Lin, Ray-Lin Wan +2 more | 1998-07-28 |
| 5699298 | Flash memory erase with controlled band-to-band tunneling current | Tzeng-Huei Shiau, Ray-Lin Wan, Yuan-Chang Liu, Chun-Hsiung Hung, Weitong Chuang +1 more | 1997-12-16 |