Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8181138 | Generation of an extracted timing model file | Richard K. Kirchner, Sandeep Bhutsuni | 2012-05-15 |
| 7689965 | Generation of an extracted timing model file | Richard K. Kirchner, Sandeep Bhutani | 2010-03-30 |
| 7577928 | Verification of an extracted timing model file | Richard K. Kirchner, Sandeep Bhutani | 2009-08-18 |
| 7406669 | Timing constraints methodology for enabling clock reconvergence pessimism removal in extracted timing models | — | 2008-07-29 |
| 6658628 | Developement of hardmac technology files (CLF, tech and synlib) for RTL and full gate level netlists | Robert E. Landy, Michael Porter, Craig R. Lang | 2003-12-02 |