VS

Virinder Singh

Lsi Logic: 3 patents #574 of 1,957Top 30%
Overall (All Time): #1,618,416 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6457157 I/O device layout during integrated circuit design Mike Liang 2002-09-24
6243849 Method and apparatus for netlist filtering and cell placement Mike Liang 2001-06-05
6057169 Method for I/O device layout during integrated circuit design Mike Liang 2000-05-02