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Method and system for designing a probe card |
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Method and system for designing a probe card |
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Automated system for designing and testing a probe card |
Benjamin N. Eldridge, Mark W. Brandemuehl, Yves Parent |
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Buffer cell insertion and electronic design automation |
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Method and system for designing a probe card |
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Utilizing a technology-independent system description incorporating a metal layer dependent attribute |
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2004-02-03 |
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Delay/load estimation for use in integrated circuit design |
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2003-10-14 |
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Static timing analysis validation tool for ASIC cores |
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2003-07-22 |
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Integrated circuit having on-chip capacitors for supplying power to portions of the circuit requiring high-transient peak power |
Shalini Rubdi, Juergen Lahner |
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Cell interconnect delay library for integrated circuit design |
Benjamin Mbouombouo, Juergen Lahner |
2003-03-11 |
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Circuit modeling |
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2002-12-31 |
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Iterative prediction of circuit delays |
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2002-09-24 |
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Clock distribution network planning and method therefor |
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2001-10-16 |
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Method of selecting and synthesizing metal interconnect wires in integrated circuits |
Emery Sugasawara |
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Low impact signal buffering in integrated circuits |
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Processing high-speed digital datastreams with reduced memory |
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2000-10-10 |
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2000-08-08 |
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Digital integrated circuit design system and methodology with hardware |
Quang Phan |
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Semiconductor integrated circuit failure analysis using magnetic imaging |
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Current waveform analysis for testing semiconductor devices |
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Intermediate test file conversion and comparison |
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1999-10-26 |
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Method for detecting bus shorts in semiconductor devices |
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1999-04-27 |
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Method and apparatus for scan chain with reduced delay penalty |
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1998-11-03 |
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Burn-in activity monitor |
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1998-06-23 |