Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7930219 | Method and system for designing a probe card | Benjamin N. Eldridge, Mark W. Brandemuehl, Yves Parent | 2011-04-19 |
| 7593872 | Method and system for designing a probe card | Benjamin N. Eldridge, Mark W. Brandemuehl, Yves Parent | 2009-09-22 |
| 7092902 | Automated system for designing and testing a probe card | Benjamin N. Eldridge, Mark W. Brandemuehl, Yves Parent | 2006-08-15 |
| 6766499 | Buffer cell insertion and electronic design automation | Benjamin Mbouombouo, Juergen Lahner | 2004-07-20 |
| 6714828 | Method and system for designing a probe card | Benjamin N. Eldridge, Mark W. Brandemuehl, Yves Parent | 2004-03-30 |
| 6687661 | Utilizing a technology-independent system description incorporating a metal layer dependent attribute | Emery Sugasawara | 2004-02-03 |
| 6634014 | Delay/load estimation for use in integrated circuit design | Grant Lindberg | 2003-10-14 |
| 6598213 | Static timing analysis validation tool for ASIC cores | — | 2003-07-22 |
| 6546538 | Integrated circuit having on-chip capacitors for supplying power to portions of the circuit requiring high-transient peak power | Shalini Rubdi, Juergen Lahner | 2003-04-08 |
| 6532576 | Cell interconnect delay library for integrated circuit design | Benjamin Mbouombouo, Juergen Lahner | 2003-03-11 |
| 6502230 | Circuit modeling | Sheela R. Shreedharan | 2002-12-31 |
| 6457160 | Iterative prediction of circuit delays | Floyd Kendrick | 2002-09-24 |
| 6305001 | Clock distribution network planning and method therefor | — | 2001-10-16 |
| 6189131 | Method of selecting and synthesizing metal interconnect wires in integrated circuits | Emery Sugasawara | 2001-02-13 |
| 6184711 | Low impact signal buffering in integrated circuits | Oscar M. Siguenza | 2001-02-06 |
| 6131151 | Processing high-speed digital datastreams with reduced memory | — | 2000-10-10 |
| 6102962 | Method for estimating quiescent current in integrated circuits | Emery Sugasawara | 2000-08-15 |
| 6101329 | System for comparing counter blocks and flag registers to determine whether FIFO buffer can send or receive data | — | 2000-08-08 |
| 6083269 | Digital integrated circuit design system and methodology with hardware | Quang Phan | 2000-07-04 |
| 6064220 | Semiconductor integrated circuit failure analysis using magnetic imaging | Emery Sugasawara | 2000-05-16 |
| 6037796 | Current waveform analysis for testing semiconductor devices | Emery Sugasawara | 2000-03-14 |
| 5974248 | Intermediate test file conversion and comparison | — | 1999-10-26 |
| 5898705 | Method for detecting bus shorts in semiconductor devices | — | 1999-04-27 |
| 5831993 | Method and apparatus for scan chain with reduced delay penalty | — | 1998-11-03 |
| 5771267 | Burn-in activity monitor | Ludger F. Johanterwage | 1998-06-23 |