| 8745457 |
Methods and structure for utilizing external interfaces used during normal operation of a circuit to output test signals |
Eugene Saghi, Joshua P. Sinykin, Jeffrey K. Whitt |
2014-06-03 |
| 8738979 |
Methods and structure for correlation of test signals routed using different signaling pathways |
Jeffrey K. Whitt, Eugene Saghi, Douglas J. Saxon, Joshua P. Sinykin |
2014-05-27 |
| 7719368 |
Configurable reset circuit for a phase-locked loop |
Travis Bradfield, Jeffrey K. Whitt |
2010-05-18 |
| 7617428 |
Circuits and associated methods for improved debug and test of an application integrated circuit |
Brad D. Besmer, Guy W. Kendall |
2009-11-10 |
| 7028233 |
Characteristic image of electrical data bus |
Andrew Hadley, Steven Olson, Jeffrey K. Whitt |
2006-04-11 |
| 6647027 |
Method and apparatus for multi-channel data delay equalization |
Frank Gasparik |
2003-11-11 |
| 6560716 |
System for measuring delay of digital signal using clock generator and delay unit wherein a set of digital elements of clock generator identical to a set of digital elements of delay unit |
Frank Gasparik |
2003-05-06 |
| 6459313 |
IO power management: synchronously regulated output skew |
Joy F. Godbee, Coralyn S. Gauvin |
2002-10-01 |
| 6446248 |
Spare cells placement methodology |
Richard Solomon |
2002-09-03 |
| 6292409 |
System for programmable chip initialization |
— |
2001-09-18 |
| 5905744 |
Test mode for multifunction PCI device |
Brian G. Reise |
1999-05-18 |
