KY

Kwok Ming Yue

Lsi Logic: 3 patents #574 of 1,957Top 30%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
CS Candence Design Systems: 1 patents #1 of 20Top 5%
📍 Fremont, CA: #3,076 of 9,298 inventorsTop 35%
🗺 California: #106,790 of 386,348 inventorsTop 30%
Overall (All Time): #1,023,269 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
8074187 Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout Judd Matthew Ylinen 2011-12-06
7694258 Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout Judd Matthew Ylinen 2010-04-06
5825659 Method for local rip-up and reroute of signal paths in an IC design Lieu T. Nguyen 1998-10-20
5686845 Hierarchial clock distribution system and method Apo C. Erdal, Trung Nguyen 1997-11-11
5570045 Hierarchical clock distribution system and method Apo C. Erdal, Trung Nguyen 1996-10-29