JY

Judd Matthew Ylinen

CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
CS Candence Design Systems: 1 patents #1 of 20Top 5%
📍 San Francisco, CA: #9,535 of 26,999 inventorsTop 40%
🗺 California: #124,610 of 386,348 inventorsTop 35%
Overall (All Time): #1,239,872 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
8074187 Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout Kwok Ming Yue 2011-12-06
8015529 Methods and apparatus for diagonal route shielding Alexander Khainson 2011-09-06
7694258 Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout Kwok Ming Yue 2010-04-06
7571408 Methods and apparatus for diagonal route shielding Alexander Khainson 2009-08-04