Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7042971 | Delay-locked loop with built-in self-test of phase margin | Ian MacPherson Flanagan, Roger Roisen, Dayanand K. Reddy | 2006-05-09 |
| 6636979 | System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays | Dayanand K. Reddy, Ian MacPherson Flanagan | 2003-10-21 |