Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7042971 | Delay-locked loop with built-in self-test of phase margin | Roger Roisen, Dayanand K. Reddy, Joel J. Christiansen | 2006-05-09 |
| 6636979 | System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays | Dayanand K. Reddy, Joel J. Christiansen | 2003-10-21 |
| 6262634 | Phase-locked loop with built-in self-test of phase margin and loop gain | Dayanand K. Reddy | 2001-07-17 |