CD

Carlos Dangelo

Lsi Logic: 29 patents #21 of 1,957Top 2%
NA Nanoconduction: 4 patents #1 of 7Top 15%
Samsung: 2 patents #37,631 of 75,807Top 50%
NASA: 1 patents #1,418 of 3,881Top 40%
Overall (All Time): #94,936 of 4,157,543Top 3%
36
Patents All Time

Issued Patents All Time

Showing 25 most recent of 36 patents

Patent #TitleCo-InventorsDate
8080871 Carbon nanotube-based structures and methods for removing heat from solid-state devices Ephraim Suhir, Subrata Dey, Barbara Wacker, Yuan Xu, Arthur Boren +4 more 2011-12-20
8039953 System and method using self-assembled nano structures in the design and fabrication of an integrated circuit micro-cooler 2011-10-18
7784531 Nanoengineered thermal materials based on carbon nanotube array composites Jun Li, Meyya Meyyappan 2010-08-31
7732918 Vapor chamber heat sink having a carbon nanotube fluid interface Jason Spitzer 2010-06-08
7656027 In-chip structures and methods for removing heat from integrated circuits Bala Padmakumar 2010-02-02
7538422 Integrated circuit micro-cooler having multi-layers of tubes of a CNT array Darin Scott Olson 2009-05-26
7109581 System and method using self-assembled nano structures in the design and fabrication of an integrated circuit micro-cooler Meyya Meyyappan, Jun Li 2006-09-19
6470482 METHOD AND SYSTEM FOR CREATING, DERIVING AND VALIDATING STRUCTURAL DESCRIPTION OF ELECTRONIC SYSTEM FROM HIGHER LEVEL, BEHAVIOR-ORIENTED DESCRIPTION, INCLUDING INTERACTIVE SCHEMATIC DESIGN AND SIMULATION Michael D. Rostoker, Daniel Watkins 2002-10-22
6324678 Method and system for creating and validating low level description of electronic design Richard Deeley, Vijay Nagasamy, Manoucher Vafai 2001-11-27
6216252 Method and system for creating, validating, and scaling structural description of electronic device Doron Mintz, Manouchehr Vafai 2001-04-10
5946487 Object-oriented multi-media architecture 1999-08-31
5933356 Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models Michael D. Rostoker, Owen S. Bair 1999-08-03
5910897 Specification and design of complex digital systems Vijay Nagasamy 1999-06-08
5898677 Integrated circuit device having a switched routing network Richard Deeley 1999-04-27
5880971 Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from semantic specifications and descriptions thereof Vijay Nagasamy, Ahsan Bootehsaz, Sreeranga P. Rajan 1999-03-09
5870308 Method and system for creating and validating low-level description of electronic design Vijay Nagasamy, Vijayanand Ponukumati 1999-02-09
5838163 Testing and exercising individual, unsingulated dies on a wafer Michael D. Rostoker, James S. Koford 1998-11-17
5801958 Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information Daniel Watkins, Doron Mintz 1998-09-01
5665989 Programmable microsystems in silicon 1997-09-09
5648661 Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies Michael D. Rostoker, James S. Koford, Edwin M. Fulcher 1997-07-15
5615126 High-speed internal interconnection technique for integrated circuits that reduces the number of signal lines through multiplexing Richard Deeley 1997-03-25
5598344 Method and system for creating, validating, and scaling structural description of electronic device Doron Mintz, Manouchehr Vafai 1997-01-28
5572437 Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models Michael D. Rostoker, Owen S. Bair 1996-11-05
5572436 Method and system for creating and validating low level description of electronic design Vijay Nagasamy, Vijayanand Ponukumati 1996-11-05
5557531 Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation Michael D. Rostoker, Vijay Nagasamy 1996-09-17